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PRELIMINARY
CY2283
Pentium(R)/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs
Features
* Mixed 2.5V and 3.3V operation * Complete clock solution for Pentium(R) /II, Cyrix 6x86, and AMD K6 processor-based motherboards -- Four CPU clocks at 2.5V or 3.3V -- Twelve 3.3V SDRAM clocks[1] -- Five synchronous PCI clocks, one free-running -- One 3.3V 48 MHz USB clock -- One 3.3V Ref. clock at 14.318 MHz -- Two AGP clocks at 3.3V * Support for ALI (-1 option) and VIA (-2 option) * I2CTM Serial Configuration Interface * Full EMI control with factory-EPROM programmable output drive and slew rate * Factory-EPROM programmable CPU clock frequencies for custom configurations * Power-down, CPU stop, and PCI stop pins * Available in space-saving 48-pin SSOP package SDRAM outputs in place of the CY2283 and can be placed in close proximity to the SDRAM modules. The CY2283 possesses power-down, CPU stop, and PCI stop pins for power management control. These inputs are multiplexed with SDRAM clock outputs, and are selected when the MODE pin is driven LOW. Additionally, the signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2283 outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2283 Selector Guide
Clock Outputs CPU (66.6, 75, 83.3, 100MHz) SDRAM PCI (30, 33.3 MHz) USB (48MHz) AGP (66.6, 60MHz) Ref. (14.318 MHz) CPU-PCI delay AGP clock -1 (ALI V) 4 12
[1]
Functional Description
The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix, or AMD processor-based PCs using the ALI Aladdin V (-1 option) or VIA MVP3 (-2 option) chipset. The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI clocks is free-running. Additionally, the part outputs twelve 3.3V SDRAM clocks[1], one 3.3V USB clock at 48 MHz, and one 3.3V reference clock at 14.318 MHz. Finally, the part outputs two AGP clocks running at 66.66 MHz or 60 MHz. The CY2283 has the flexibility to work as either a one-chip or as part of a two-chip clocking solution. In 100-MHz board designs based on the ALI Aladdin V chipset, it is recommended that the CY2283 be used with an external SDRAM buffer solution such as the CY2318NZ or CY2314NZ. In this configuration the SDRAM outputs on the CY2283 must be either turned off using I2C or left floating. The CY231xNZ family provides the
-2 (VIA MVP3) 4 12 5[2] 1 2 1 2.5-5.5 ns In phase with CPU
5[2] 1 2 1 2.5-5.5 ns In phase with PCI
Notes: 1. SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the ALI V chipset, an external CY231xNZ buffer should be used. 2. One free-running PCI clock
Logic Block Diagram
XTALIN
XTALOUT
Pin Configuration (48 SSOP)
REF0 (14.318 MHz)
AVDD REF0 CPU PLL STOP LOGIC VSS XTALIN XTALOUT VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 AGP0 VDDQ3 AGP1 VSS SDRAM11 SDRAM10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 CY2283-1,-2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 USBCLK SEL1 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5/PWR_DWN VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP VSS SEL0 MODE
14.318 MHz OSC.
CPUCLK [0-3] VDDCPU
SEL0 SEL1 MODE
EPROM
SDRAM5/PWR_DWN SDRAM [0-4],[8-11] SDRAM6/CPU_STOP
Delay (-2 option) SYS PLL /1, /1.25, /1.5
SDRAM7/PCI_STOP AGP
Delay (-1 option) /2 STOP LOGIC
PCI [0-3] PCICLK_F
VDDQ3 SDRAM9 SDRAM8 VSS SDATA SCLK
SCLK SDATA
SERIAL INTERFACE CONTROL LOGIC
USBCLK
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 October 12, 1998
PRELIMINARY
Pin Summary
Name VDDQ3 VDDCPU AVDD VSS XTALIN[3] XTALOUT
[3]
CY2283
Pins 42 1 3, 9, 16, 22, 27, 33, 39, 45 4 5 28 29 31 38, 37, 35, 34, 32, 21, 20, 18, 17 26 46 44, 43, 41, 40 8, 10, 11, 12 7 13, 15 2 47 23 24 25
Description CPU Digital voltage supply, 2.5V or 3.3V Analog voltage supply, 3.3V Ground Reference crystal input Reference crystal feedback SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled when MODE is LOW. SDRAM clock output. Also, active LOW control input to stop CPU clocks, enabled when MODE is LOW. SDRAM clock output. Also, active LOW control input to power down device, enabled when MODE is LOW. SDRAM clock outputs CPU frequency select input, bit 0 (see table below) CPU frequency select input, bit 0 (see table below) CPU clock outputs PCI clock outputs, at one-half the CPU frequency. Free-running PCI clock output AGP clock outputs 3.3V Reference clock output USB Clock output Serial data input for serial configuration port Serial clock input for serial configuration port Mode Select pin for enabling power management features
6, 14, 19, 30, 36, 48 3.3V Digital voltage supply
SDRAM7/ PCI_STOP SDRAM6/CPU_STOP SDRAM5/ PWR_DWN SDRAM[0:4],[8:11] SEL0 SEL1 CPUCLK[0:3] PCICLK[0:3] PCICLK_F AGP[0:1] REF0 USBCLK SDATA SCLK MODE
Note: 3. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Function Table
SEL1 0 0 1 1 SEL0 0 1 0 1 2 3.0 2.5 CPU/PCI Ratio 2.5 CPUCLK[0:3] SDRAM[0:11] 83.33 MHz 66.67 MHz 100.0 MHz 75.0 MHz PCICLK[0:3] PCICLK_F 33.33 MHz 33.33 MHz 33.33 MHz 30.0 MHz AGP[0:1] 66.66 MHz 66.66 MHz 66.66 MHz 60.0 MHz REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USBCLK 48 MHz 48 MHz 48 MHz 48 MHz
2
PRELIMINARY
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK CPUCLK CPUCLK USBCLK Target Frequency (MHz) 66.67 75.0 83.33 100.0 48.0 Actual Frequency (MHz) 66.51 75.0 83.14 99.77 48.01 0 -2346 -2346 167 PPM -2346
CY2283
CPU and PCI Clock Driver Strengths
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V
Power Management Logic[4] - Active when MODE pin is held `LOW'
CPU_STOP PCI_STOP X 0 0 1 1 X 0 1 0 1 PWR_DWN 0 1 1 1 1 Low Low Low 66/75/83/100MHz 66/75/83/100MHz CPUCLK PCICLK Low Low 33/30 MHz Low 30/33.3 MHz PCICLK_F Stopped Running Running Running Running Other Clocks Stopped Running Running Running Running Osc. Off PLLs Off
Running Running Running Running Running Running Running Running
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * I2C Address for the CY2283 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ----
Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable)
Bit Pin # Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' Bit 1 1 1 0 0 Bit 0 1 - Three-State 0 - N/A 1 - Testmode 0 - Normal Operation Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 -Bit 2 -Bit 1 -Bit 0
Select Functions
Outputs Functional Description Three-State Test Mode[6] CPU Hi-Z TCLK/2[5] PCI, PCI_F Hi-Z TCLK/4 SDRAM Hi-Z TCLK/2 Ref Hi-Z TCLK IOAPIC Hi-Z TCLK USBCLK Hi-Z TCLK/2 AGP Hi-Z TCLK/2
Notes: 4. AGP clocks are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table. 5. TCLK supplied on the XTALIN pin in Test Mode. 6. Valid only for SEL1=0.
3
PRELIMINARY
Byte 1: CPU Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 N/A N/A N/A 40 41 43 44 USBCLK (Reserved) drive to `0' (Reserved) drive to `0' Not used - drive to `0' CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive) CPUCLK0 (Active/Inactive) Description
CY2283
Byte 2: PCI Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -7 15 14 12 11 10 8 Pin # Description (Reserved) drive to `0' PCICLK_F (Active/Inactive) AGP1 (Active/Inactive) AGP0 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 28 Bit 6 29 Bit 5 31 Bit 4 32 Bit 3 34 Bit 2 35 Bit 1 37 Bit 0 38
Byte 4: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A 17 18 20 21 Description Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' SDRAM11 SDRAM10 SDRAM9 SDRAM8
Byte 5: Peripheral Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A N/A N/A N/A 2 Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved), drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' REF0 (Active/Inactive)
Byte 6: Reserved, for future use
4
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
CY2283
Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[7]
Parameter AVDD, V DDQ3 VDDCPU TA CL CPU Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, USBCLK, IOAPIC PCICLK, AGP, SDRAM REF0 Reference Frequency, Oscillator Nominal Value Description Analog and Digital Supply Voltage Min. 3.135 2.375 3.135 0 10 20 20 14.318 Max. 3.465 2.9 3.465 70 20 30 45 14.318 MHz Unit V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs I2C inputs only IOH = 16 mA CPUCLK IOH = 18 mA IOAPIC Low-level Output Voltage VDDCPU = VDDQ2 = 2.375V IOL = 27 mA CPUCLK IOL = 29 mA IOAPIC High-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V IOH = 16 mA CPUCLK IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 26 mA USBCLK IOH = 36 mA REF0 VOL Low-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V IOL = 27 mA CPUCLK IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 21 mA USBCLK IOL = 29 mA REF0 IIH IIL IOZ IDD IDD IDDS Input High Current Input Low Current Output Leakage Current Power Supply Current[8] Power Supply Current[8] Power-down Current VIH = V DD VIL = 0V Three-state VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs, CPU clocks = 66.67 MHz VDD = 3.465V, V IN = 0 or VDD, Unloaded Outputs Current draw in power-down state -10 -10 +10 10 +10 300 120 500 A A A mA mA A 0.4V V 2.4 V 0.4 V 2.0 Test Conditions Min. Max. Unit 2.0 0.8 0.7 V V V V
High-level Output Voltage VDDCPU = VDDQ2 = 2.375V
Notes: 7. Electrical parameters are guaranteed with these operating conditions. 8. Power supply current will vary with number of outputs that are running.
5
PRELIMINARY
CY2283
Switching Characteristics for CY2283-1[9, 10]
Parameter t1 t2 t2 t2 t3 t4 t5 t6 t8 t9 t10 t10 t10 t11 Output All CPUCLK AGP, REF0 PCI CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK PCICLK, PCICLK PCICLK, AGP CPUCLK PCICLK AGP CPUCLK, PCICLK, AGP Description Output Duty Cycle
[11]
Test Conditions t1 = t1A / t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, VDDCPU = 3.3V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI, AGP clock stabilization from power-up
Min. 45 0.75 0.85 0.85 0.4 0.5 0.4 0.5
Typ. 50
Max. 55 4.0 4.0 4.0 2.13 2.67 2.13 2.67
Unit % V/ns V/ns V/ns ns ns ps ns ps ps ps ps ps ms
CPU Clock Rising and Falling Edge Rate AGP, REF0 Clock Rising and Falling Edge Rate PCI Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew PCI-PCI Clock Skew PCI-AGP Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
100 2.5 3.5
500 5.5 500 1,200 500 750 800 3
Notes: 9. Guaranteed by Design and Characterization, not 100% tested in production. 10. Device characterized and parameters guaranteed with SDRAM outputs turned off. All other outputs at maximum load. 11. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
6
PRELIMINARY
Switching Characteristics for CY2283-2
Parameter t1 t2 t2 All CPUCLK SDRAM, AGP, REF0 PCI CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM PCICLK, PCICLK PCICLK, AGP CPUCLK, SDRAM PCICLK AGP CPUCLK, PCICLK, AGP,SDRAM Output Description Output Duty Cycle CPU Clock Rising and Falling Edge Rate SDRAM, AGP, REF0 Clock Rising and Falling Edge Rate PCI Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew PCI-PCI Clock Skew PCI-AGP Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time Test Conditions t1 = t1A / t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Min. TBD TBD TBD Typ. TBD TBD TBD
CY2283
Max. TBD TBD TBD
Unit % V/ns V/ns
t2 t3 t4 t5 t6 t7 t8 t9 t10 t10 t10 t11
Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, V DDCPU = 3.3V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI, AGP, and SDRAM clock stabilization from power-up
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
V/ns ns ns ps ns ps ps ps ps ps ps ms
Timing Requirement for the I2C Bus
Parameter t12 t13 t14 t15 t16 t17 t18 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The LOW period of the clock The HIGH period of the clock Set-up time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters for I2C devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Set-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns s ns s Max. 100 Unit kHz s s s s s s
t19 t20 t21 t22
7
PRELIMINARY
Switching Waveforms
Duty Cycle Timing
t1A OUTPUT t1B
CY2283
All Outputs Rise/Fall Time
VDD OUTPUT t2 t3 t2 t4 0V
CPU-CPU Clock Skew
CPUCLK
CPUCLK t5
CPU-SDRAM Clock Skew
CPUCLK
SDRAM t7
CPU-PCI Clock Skew
CPUCLK
PCICLK t6
PCI-PCI Clock Skew
PCICLK
PCICLK t8
8
PRELIMINARY
Switching Waveforms (continued)
AGP-PCI Clock Skew
AGPCLK
CY2283
PCICLK t9
CPU_STOP[12, 13]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External)
PCI_STOP[14, 15]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the I2C Bus
SDA
t13 SCL t14 t15
t20
t21
t14
t18
t16
t19
t17
t22
Notes: 12. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 13. CPU_STOP may be applied asynchronously. It is synchronized internally. 14. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 15. PCI_STOP may be applied asynchronously. It is synchronized internally.
9
PRELIMINARY
Application Circuit
Clock traces must be terminated with either series or parallel termination, as they are normally done
CY2283
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
10
PRELIMINARY
CY2283
Test Circuit
VDDQ3
1 0.1 F 3
48 0.1 F 45
6 0.1 F 9 39 14 0.1 F CY2283-1,-2 42 0.1 F
VDDCPU
36
0.1 F
16
33 30 0.1 F 27
0.1 F
19
22
OUTPUTS CLOAD Note: All Capacitors must be placed as close to the pins as is possible
Ordering Information
Ordering Code CY2283PVC-1 CY2283PVC-2 Document #: 38-00685-A Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation. Package Name O48 O48 Package Type 48-Pin SSOP 48-Pin SSOP Operating Range Commercial Commercial
11
PRELIMINARY
Package Diagram
48-Lead Shrunk Small Outline Package O48
CY2283
51-85061-B
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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